As technology has advanced, a trend has developed to place an increasingly large number of IO signals on a chip. To handle the large number of IO signals, an increased number of designers are using the flip-chip design as a solution. Embodiments of the present invention are directed to special routing on the flip-chip design.
In a typical flip-chip design, there are many bump IO pins placed in the middle of the chip, and the IO pad cells are placed peripherally around the chip. To connect the bump pins with the IO cell pins, usually stack vias are dropped on the IO pin to the upper layer and then router route from the vias to the bump pins. The layer used to do the routing is called a redistribution layer (RDL), and the routing is called RDL routing. FIG. 1 shows an example diagram of a flip-chip design.
For RDL routing, there are different requirements for the nets. One of the requirements is the differential group routing. There are two types of differential group routing; one is length matching and the other is pattern matching. FIG. 2 illustrates a diagram exemplifying length matching and pattern matching. For a group of multiple special signal nets, it is required that the resistance or impedance matches, thus length matching can achieve this goal. For some other more sensitive signal groups, besides the length needing to match, it may also be required to have pattern matching, such that during signal transition, electromagnetic noise can be further reduced. Embodiments described herein are directed to differential group routing with pattern match for RDL routing.